Metastability-Containing Circuits

In digital circuits, metastable signals have voltages strictly between logical 0 and logical~1, breaking the abstraction of Boolean logic. Unfortunately, any way of reading a signal from an unsynchronized clock domain or performing an analog-to-digital conversion incurs the risk of a metastable result; no physical implementation of a digital circuit can deterministically avoid, resolve, or detect metastability (Marino, 1981). Traditionally, the only countermeasure is to write a potentially metastable signal into a synchronizer---a bistable storage element like a flip-flop---and wait. Synchronizers exponentially decrease the odds of maintained metastability over time, i.e., the waiting time determines the probability to resolve to logical 0 or 1. Accordingly, this approach delays subsequent computations and does not guarantee success. We propose a fundamentally different approach: It is possible to contain metastability by fine-grained logical masking so that it cannot infect the entire circuit. This technique guarantees a limited degree of metastability in---and uncertainty about---the output. At the heart of our approach lies a model for metastability in synchronous clocked digital circuits. Metastability is propagated in a worst-case fashion, allowing to derive deterministic guarantees, without and unlike synchronizers. We fully classify which functions can be computed by synchronous, clocked, digital circuits with standard registers. Regarding masking registers, we show that they become computationally strictly more powerful with each clock cycle, resulting in a non-trivial hierarchy of computable functions. Furthermore, while permitting positive results, the proposed model passes the test of reproducing Marino's physical impossibility results regarding avoidance, resolution, and detection of metastability.