Contemporary Processors Are Leaky -- and There's Nothing You Can Do About It

We measure capacities of known and suspected microarchitectural timing channels across the two mainstream processor architectures, x86 and ARM, and along several generations of Intel and ARM processor implementations, with release dates ranging from 2007 to 2015. We then apply all flushing mechanisms provided by the architectures in an attempt to close those channels, irrespective of cost. We find that in all processors we studied, at least one significant channel remains: the one exploited by an I-cache attack (although the underlying mechanisms are likely more complex than just the I-cache). In short, closing all timing channels seems impossible on contemporary main-stream processors.