PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruning

IEEE transactions on computers (IEEE Trans. Comput.), 2025

14 January 2025

Papers citing "PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruning"

2 / 2 papers shown

Title
Light Differentiable Logic Gate Networks Lukas Rüttgers Till Aczél Andreas Plesner Roger Wattenhofer 36 0 0 26 Sep 2025
NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT InferenceIEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), 2025 Marta Andronic George A. Constantinides 224 3 0 01 Apr 2025