Adding numbers with spiking neural circuits on neuromorphic hardware: A building block for future hybrid systems

Progress in neuromorphic computing requires efficient implementation of standard computational problems, like adding numbers. Here we implement a variety of sequential and parallel binary adders in the Lava software framework, and deploy them to the neuromorphic chip Loihi 2. To the best of our knowledge, up to now, a neuromorphic implementation of such parallel adders has not been reported. We describe the time complexity, neuron and synaptic resources, as well as constraints on the bit width of the numbers that can be added with the current implementations. Further, we measure the time required for the addition operation on-chip. Importantly, we encounter trade-offs in terms of time complexity and required chip resources for the three considered adders. While sequential adders have linear time complexity $\mathcal{O}(n)$ and require a linearly increasing number of neurons and synapses with number of bits $n$, the parallel adders have constant time complexity $\mathcal{O}(1)$ and also require a linearly increasing number of neurons, but nonlinearly increasing synaptic resources (scaling with $n^2$ or $n \sqrt{n}$). This trade-off between compute time and chip resources may inform decisions in application development, and the implementations we provide may serve as a building block for further progress towards efficient neuromorphic algorithms.