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A parallel pattern for iterative stencil + reduce

A parallel pattern for iterative stencil + reduce

15 September 2016
Marco Aldinucci
Marco Danelutto
M. Drocco
Peter Kilpatrick
Claudia Misale
G. P. Pezzi
Massimo Torquati
ArXiv (abs)PDFHTML

Papers citing "A parallel pattern for iterative stencil + reduce"

1 / 1 papers shown
Accelerating Green Computing with Hybrid Asymmetric Multicore
  Architectures and Safe Parallelism
Accelerating Green Computing with Hybrid Asymmetric Multicore Architectures and Safe Parallelism
Hope Mogale
M. Esiefarienrhe
N. Gasela
Lucia Letlonkane
120
1
0
19 Sep 2019
1
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