ResearchTrend.AI
  • Papers
  • Communities
  • Events
  • Blog
  • Pricing
Papers
Communities
Social Events
Terms and Conditions
Pricing
Parameter LabParameter LabTwitterGitHubLinkedInBlueskyYoutube

© 2025 ResearchTrend.AI, All rights reserved.

  1. Home
  2. Papers
  3. 1612.07119
  4. Cited By
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference

FINN: A Framework for Fast, Scalable Binarized Neural Network Inference

1 December 2016
Yaman Umuroglu
Nicholas J. Fraser
Giulio Gambardella
Michaela Blott
Philip H. W. Leong
Magnus Jahre
K. Vissers
    MQ
ArXivPDFHTML

Papers citing "FINN: A Framework for Fast, Scalable Binarized Neural Network Inference"

29 / 79 papers shown
Title
Edge AI: On-Demand Accelerating Deep Neural Network Inference via Edge
  Computing
Edge AI: On-Demand Accelerating Deep Neural Network Inference via Edge Computing
En Li
Liekang Zeng
Zhi Zhou
Xu Chen
4
614
0
04 Oct 2019
REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object
  Detection on FPGAs
REQ-YOLO: A Resource-Aware, Efficient Quantization Framework for Object Detection on FPGAs
Caiwen Ding
Shuo Wang
Ning Liu
Kaidi Xu
Yanzhi Wang
Yun Liang
MQ
16
89
0
29 Sep 2019
Accurate and Compact Convolutional Neural Networks with Trained
  Binarization
Accurate and Compact Convolutional Neural Networks with Trained Binarization
Zhe Xu
R. Cheung
MQ
19
54
0
25 Sep 2019
Structured Binary Neural Networks for Image Recognition
Structured Binary Neural Networks for Image Recognition
Bohan Zhuang
Chunhua Shen
Mingkui Tan
Peng Chen
Lingqiao Liu
Ian Reid
MQ
22
17
0
22 Sep 2019
Unrolling Ternary Neural Networks
Unrolling Ternary Neural Networks
Stephen Tridgell
M. Kumm
M. Hardieck
David Boland
Duncan J. M. Moss
P. Zipf
Philip H. W. Leong
19
26
0
09 Sep 2019
A Novel Design of Adaptive and Hierarchical Convolutional Neural
  Networks using Partial Reconfiguration on FPGA
A Novel Design of Adaptive and Hierarchical Convolutional Neural Networks using Partial Reconfiguration on FPGA
Mohammad Farhadi
Mehdi Ghasemi
Yezhou Yang
6
27
0
05 Sep 2019
Effective Training of Convolutional Neural Networks with Low-bitwidth
  Weights and Activations
Effective Training of Convolutional Neural Networks with Low-bitwidth Weights and Activations
Bohan Zhuang
Jing Liu
Mingkui Tan
Lingqiao Liu
Ian Reid
Chunhua Shen
MQ
26
44
0
10 Aug 2019
Evolutionary Cell Aided Design for Neural Network Architectures
Evolutionary Cell Aided Design for Neural Network Architectures
Philip Colangelo
Oren Segal
Alexander Speicher
M. Margala
6
3
0
06 Mar 2019
FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer
  Learning
FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning
P. Whatmough
Chuteng Zhou
Patrick Hansen
S. Venkataramanaiah
Jae-sun Seo
Matthew Mattina
15
57
0
27 Feb 2019
CodeX: Bit-Flexible Encoding for Streaming-based FPGA Acceleration of
  DNNs
CodeX: Bit-Flexible Encoding for Streaming-based FPGA Acceleration of DNNs
Mohammad Samragh
Mojan Javaheripi
F. Koushanfar
30
11
0
17 Jan 2019
ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using
  Alternating Direction Method of Multipliers
ADMM-NN: An Algorithm-Hardware Co-Design Framework of DNNs Using Alternating Direction Method of Multipliers
Ao Ren
Tianyun Zhang
Shaokai Ye
Jiayu Li
Wenyao Xu
Xuehai Qian
X. Lin
Yanzhi Wang
MQ
29
162
0
31 Dec 2018
Structured Binary Neural Networks for Accurate Image Classification and
  Semantic Segmentation
Structured Binary Neural Networks for Accurate Image Classification and Semantic Segmentation
Bohan Zhuang
Chunhua Shen
Mingkui Tan
Lingqiao Liu
Ian Reid
MQ
27
152
0
22 Nov 2018
Combinatorial Attacks on Binarized Neural Networks
Combinatorial Attacks on Binarized Neural Networks
Elias Boutros Khalil
Amrita Gupta
B. Dilkina
AAML
41
40
0
08 Oct 2018
Towards Fast and Energy-Efficient Binarized Neural Network Inference on
  FPGA
Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA
Cheng Fu
Shilin Zhu
Hao Su
Ching-En Lee
Jishen Zhao
MQ
15
31
0
04 Oct 2018
Towards Efficient Convolutional Neural Network for Domain-Specific
  Applications on FPGA
Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA
Ruizhe Zhao
Ho-Cheung Ng
Wayne Luk
Xinyu Niu
14
34
0
04 Sep 2018
Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural
  Network in Embedded FPGA
Design Flow of Accelerating Hybrid Extremely Low Bit-width Neural Network in Embedded FPGA
Junsong Wang
Qiuwen Lou
Xiaofan Zhang
Chao Zhu
Yonghua Lin
Deming Chen
MQ
28
93
0
31 Jul 2018
FINN-L: Library Extensions and Design Trade-off Analysis for Variable
  Precision LSTM Networks on FPGAs
FINN-L: Library Extensions and Design Trade-off Analysis for Variable Precision LSTM Networks on FPGAs
Vladimir Rybalkin
Alessandro Pappalardo
M. M. Ghaffar
Giulio Gambardella
Norbert Wehn
Michaela Blott
11
72
0
11 Jul 2018
XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary
  Neural Network Inference
XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference
Francesco Conti
Pasquale Davide Schiavone
Luca Benini
24
108
0
09 Jul 2018
Inference of Quantized Neural Networks on Heterogeneous All-Programmable
  Devices
Inference of Quantized Neural Networks on Heterogeneous All-Programmable Devices
Thomas B. Preußer
Giulio Gambardella
Nicholas J. Fraser
Michaela Blott
MQ
24
41
0
21 Jun 2018
Accelerating CNN inference on FPGAs: A Survey
Accelerating CNN inference on FPGAs: A Survey
K. Abdelouahab
Maxime Pelcat
Jocelyn Serot
F. Berry
AI4CE
22
147
0
26 May 2018
Synergy: A HW/SW Framework for High Throughput CNNs on Embedded
  Heterogeneous SoC
Synergy: A HW/SW Framework for High Throughput CNNs on Embedded Heterogeneous SoC
G. Zhong
Akshat Dubey
Cheng Tan
T. Mitra
15
69
0
28 Mar 2018
Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey
  and Future Directions
Toolflows for Mapping Convolutional Neural Networks on FPGAs: A Survey and Future Directions
Stylianos I. Venieris
Alexandros Kouris
C. Bouganis
11
184
0
15 Mar 2018
XNORBIN: A 95 TOp/s/W Hardware Accelerator for Binary Convolutional
  Neural Networks
XNORBIN: A 95 TOp/s/W Hardware Accelerator for Binary Convolutional Neural Networks
A. Bahou
G. Karunaratne
Renzo Andri
Lukas Cavigelli
Luca Benini
MQ
17
45
0
05 Mar 2018
Bit Fusion: Bit-Level Dynamically Composable Architecture for
  Accelerating Deep Neural Networks
Bit Fusion: Bit-Level Dynamically Composable Architecture for Accelerating Deep Neural Networks
Hardik Sharma
Jongse Park
Naveen Suda
Liangzhen Lai
Benson Chau
J. Kim
Vikas Chandra
H. Esmaeilzadeh
MQ
21
486
0
05 Dec 2017
Design Automation for Binarized Neural Networks: A Quantum Leap
  Opportunity?
Design Automation for Binarized Neural Networks: A Quantum Leap Opportunity?
Manuele Rusci
Lukas Cavigelli
Luca Benini
MQ
23
20
0
21 Nov 2017
WRPN: Wide Reduced-Precision Networks
WRPN: Wide Reduced-Precision Networks
Asit K. Mishra
Eriko Nurvitadhi
Jeffrey J. Cook
Debbie Marr
MQ
28
266
0
04 Sep 2017
Streaming Architecture for Large-Scale Quantized Neural Networks on an
  FPGA-Based Dataflow Platform
Streaming Architecture for Large-Scale Quantized Neural Networks on an FPGA-Based Dataflow Platform
Chaim Baskin
Natan Liss
Evgenii Zheltonozhskii
A. Bronstein
A. Mendelson
GNN
MQ
28
35
0
31 Jul 2017
Deep Reservoir Computing Using Cellular Automata
Deep Reservoir Computing Using Cellular Automata
Stefano Nichele
Andreas Molund
6
27
0
08 Mar 2017
Mixed Low-precision Deep Learning Inference using Dynamic Fixed Point
Mixed Low-precision Deep Learning Inference using Dynamic Fixed Point
Naveen Mellempudi
Abhisek Kundu
Dipankar Das
Dheevatsa Mudigere
Bharat Kaul
MQ
27
30
0
31 Jan 2017
Previous
12