Analog CMOS-based Resistive Processing Unit for Deep Neural Network Training

20 June 2017

Papers citing "Analog CMOS-based Resistive Processing Unit for Deep Neural Network Training"

6 / 6 papers shown

Title
Non-Ideal Program-Time Conservation in Charge Trap Flash for Deep Learning S. Shrivastava V. Saraswat G. Dash S. Chakrabarty U. Ganguly 9 2 0 12 Jul 2023
A temporally and spatially local spike-based backpropagation algorithm to enable training in hardware Anmol Biswas V. Saraswat U. Ganguly AAML 29 1 0 20 Jul 2022
TxSim:Modeling Training of Deep Neural Networks on Resistive Crossbar Systems Sourjya Roy S. Sridharan Shubham Jain A. Raghunathan 34 44 0 25 Feb 2020
On-chip learning in a conventional silicon MOSFET based Analog Hardware Neural Network N. Dey Janak Sharda Utkarsh Saxena Divya Kaushik Utkarsh Singh D. Bhowmik 6 8 0 01 Jul 2019
RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars Shubham Jain Abhronil Sengupta Kaushik Roy A. Raghunathan 38 87 0 31 Aug 2018
Training LSTM Networks with Resistive Cross-Point Devices Tayfun Gokmen Malte J. Rasch W. Haensch 13 45 0 01 Jun 2018