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Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator
31 July 2017
M. Marinella
S. Agarwal
Alexander H. Hsia
Isaac Richter
R. Jacobs-Gedrim
J. Niroula
S. Plimpton
Engin Ipek
C. James
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Papers citing
"Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator"
20 / 20 papers shown
When In-memory Computing Meets Spiking Neural Networks -- A Perspective on Device-Circuit-System-and-Algorithm Co-design
Applied Physics Reviews (APR), 2024
Abhishek Moitra
Abhiroop Bhattacharjee
Yuhang Li
Youngeun Kim
Priyadarshini Panda
298
9
0
22 Aug 2024
System-level Impact of Non-Ideal Program-Time of Charge Trap Flash (CTF) on Deep Neural Network
S. Shrivastava
A. Biswas
S. Chakrabarty
G. Dash
V. Saraswat
U. Ganguly
100
0
0
15 Feb 2024
Examining the Role and Limits of Batchnorm Optimization to Mitigate Diverse Hardware-noise in In-memory Computing
ACM Great Lakes Symposium on VLSI (GLSVLSI), 2023
Abhiroop Bhattacharjee
Abhishek Moitra
Youngeun Kim
Yeshwanth Venkatesha
Priyadarshini Panda
149
10
0
28 May 2023
Device Modeling Bias in ReRAM-based Neural Network Simulations
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JESTCAS), 2022
Osama Yousuf
Imtiaz Hossen
M. Daniels
Martin Lueker-Boden
A. Dienstfrey
G. Adam
75
5
0
29 Nov 2022
NEON: Enabling Efficient Support for Nonlinear Operations in Resistive RAM-based Neural Network Accelerators
Aditya Manglik
Minesh Patel
Haiyu Mao
Behzad Salami
Mohammad Sadrosadati
Lois Orosa
O. Mutlu
265
1
0
10 Nov 2022
An Experimental Evaluation of Machine Learning Training on a Real Processing-in-Memory System
Juan Gómez Luna
Yu-Yin Guo
Sylvan Brocard
Julien Legriel
Remy Cimadomo
Geraldo F. Oliveira
Gagandeep Singh
O. Mutlu
VLM
355
20
0
16 Jul 2022
Effect of Batch Normalization on Noise Resistant Property of Deep Learning Models
Omobayode Fagbohungbe
Lijun Qian
239
15
0
15 May 2022
On the Accuracy of Analog Neural Network Inference Accelerators
T. Xiao
Ben Feinberg
C. Bennett
V. Prabhakar
Prashant Saxena
V. Agrawal
S. Agarwal
M. Marinella
382
60
0
03 Sep 2021
H2Learn: High-Efficiency Learning Accelerator for High-Accuracy Spiking Neural Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2021
Ling Liang
Zheng Qu
Zhaodong Chen
Fengbin Tu
Yujie Wu
Lei Deng
Guoqi Li
Peng Li
Yuan Xie
228
32
0
25 Jul 2021
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs
Petar Jokic
E. Azarkhish
Andrea Bonetti
M. Pons
S. Emery
Luca Benini
252
5
0
24 Jun 2021
Prospects for Analog Circuits in Deep Networks
Shih-Chii Liu
J. Strachan
A. Basu
104
6
0
23 Jun 2021
DetectX -- Adversarial Input Detection using Current Signatures in Memristive XBar Arrays
IEEE Transactions on Circuits and Systems Part 1: Regular Papers (TCAS-I), 2021
Abhishek Moitra
Priyadarshini Panda
AAML
157
7
0
22 Jun 2021
FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator
Geng Yuan
Rohit Das
Zhengang Li
Ali Shafiee
Sheng Lin
...
Hang Liu
Xuehai Qian
M. N. Bojnordi
Yanzhi Wang
Caiwen Ding
223
79
0
16 Jun 2021
Brain-inspired computing: We need a master plan
A. Mehonic
A. Kenyon
236
521
0
29 Apr 2021
Benchmarking Inference Performance of Deep Learning Models on Analog Devices
IEEE International Joint Conference on Neural Network (IJCNN), 2020
Omobayode Fagbohungbe
Lijun Qian
242
10
0
24 Nov 2020
Device-aware inference operations in SONOS nonvolatile memory arrays
IEEE International Reliability Physics Symposium (IRPS), 2020
C. Bennett
T. Xiao
Ryan Dellana
V. Agrawal
Ben Feinberg
...
S. Saha
V. Raghavan
Ramesh Chettuvetty
S. Agarwal
M. Marinella
163
11
0
02 Apr 2020
Plasticity-Enhanced Domain-Wall MTJ Neural Networks for Energy-Efficient Online Learning
International Symposium on Circuits and Systems (ISCAS), 2020
Christopher Bennett
T. Xiao
Can Cui
Naimul Hassan
Otitoaleke G. Akinola
J. Incorvia
Alvaro Velasquez
Joseph S. Friedman
M. Marinella
106
2
0
04 Mar 2020
Evaluating complexity and resilience trade-offs in emerging memory inference machines
Neuro Inspired Computational Elements Workshop (NICE), 2020
C. Bennett
Ryan Dellana
T. Xiao
Ben Feinberg
S. Agarwal
S. Cardwell
M. Marinella
William M. Severa
Brad Aimone
154
3
0
25 Feb 2020
A Supervised Learning Algorithm for Multilayer Spiking Neural Networks Based on Temporal Coding Toward Energy-Efficient VLSI Processor Design
IEEE Transactions on Neural Networks and Learning Systems (IEEE TNNLS), 2020
Yusuke Sakemi
K. Morino
Takashi Morie
Kazuyuki Aihara
217
37
0
08 Jan 2020
PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-efficient ReRAM
IEEE transactions on computers (IEEE Trans. Comput.), 2019
Aayush Ankit
I. E. Hajj
S. R. Chalamalasetti
S. Agarwal
M. Marinella
M. Foltin
J. Strachan
D. Milojicic
Wen-mei W. Hwu
Kaushik Roy
157
80
0
24 Dec 2019
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