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1710.04094
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Validation of hardware events for successful performance pattern identification in High Performance Computing
11 October 2017
Thomas Röhl
Jan Eitzinger
G. Hager
G. Wellein
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Papers citing
"Validation of hardware events for successful performance pattern identification in High Performance Computing"
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Level-based Blocking for Sparse Matrices: Sparse Matrix-Power-Vector Multiplication
IEEE Transactions on Parallel and Distributed Systems (TPDS), 2022
C. Alappat
G. Hager
Olaf Schenk
G. Wellein
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03 May 2022
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