Structured Weight Matrices-Based Hardware Accelerators in Deep Neural
Networks: FPGAs and ASICs

Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs

28 March 2018

Caiwen Ding

Papers citing "Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs"

3 / 3 papers shown

Title
FORMS: Fine-grained Polarized ReRAM-based In-situ Computation for Mixed-signal DNN Accelerator Geng Yuan Payman Behnam Zhengang Li Ali Shafiee Sheng Lin ... Hang Liu Xuehai Qian M. N. Bojnordi Yanzhi Wang Caiwen Ding 19 68 0 16 Jun 2021
Teachers Do More Than Teach: Compressing Image-to-Image Models Qing Jin Jian Ren Oliver J. Woodford Jiazhuo Wang Geng Yuan Yanzhi Wang Sergey Tulyakov 31 54 0 05 Mar 2021
Tiny but Accurate: A Pruned, Quantized and Optimized Memristor Crossbar Framework for Ultra Efficient DNN Implementation Xiaolong Ma Geng Yuan Sheng Lin Caiwen Ding Fuxun Yu Tao Liu Wujie Wen Xiang Chen Yanzhi Wang MQ 10 45 0 27 Aug 2019