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FATE: Fast and Accurate Timing Error Prediction Framework for Low Power
  DNN Accelerator Design

FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design

2 July 2018
J. Zhang
S. Garg
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Papers citing "FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design"

1 / 1 papers shown
Title
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory
  Neural Accelerators
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators
Weiwen Jiang
Qiuwen Lou
Zheyu Yan
Lei Yang
Jiaxi Hu
X. S. Hu
Yiyu Shi
11
72
0
31 Oct 2019
1