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1904.06278
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RELOAD+REFRESH: Abusing Cache Replacement Policies to Perform Stealthy Cache Attacks
12 April 2019
Samira Briongos
Pedro Malagón
Jose M. Moya
T. Eisenbarth
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Papers citing
"RELOAD+REFRESH: Abusing Cache Replacement Policies to Perform Stealthy Cache Attacks"
25 / 25 papers shown
Title
A Distributed Emulation Environment for In-Memory Computing Systems
International Instrumentation and Measurement Technology Conference (I2MTC), 2025
Eleni Bougioukou
Anastasios Petropoulos
Nikolaos Toulgaridis
Theodoros Chatzimichail
Theodore Antonakopoulos
56
0
0
09 Oct 2025
Shield Bash: Abusing Defensive Coherence State Retrieval to Break Timing Obfuscation
K. Ramkrishnan
Antonia Zhai
Stephen McCamant
P. Yew
128
0
0
14 Apr 2025
Write+Sync: Software Cache Write Covert Channels Exploiting Memory-disk Synchronization
IEEE Transactions on Information Forensics and Security (IEEE TIFS), 2023
Congcong Chen
Jinhua Cui
Gang Qu
Jiliang Zhang
SyDa
275
0
0
17 Jan 2025
RollingCache: Using Runtime Behavior to Defend Against Cache Side Channel Attacks
Divya Ojha
S. Dwarkadas
135
0
0
16 Aug 2024
Last-Level Cache Side-Channel Attacks Are Feasible in the Modern Public Cloud (Extended Version)
Zirui Neil Zhao
Adam Morrison
Christopher W. Fletcher
Josep Torrellas
144
22
0
21 May 2024
Prime+Retouch: When Cache is Locked and Leaked
Jaehyuk Lee
Fan Sang
Taesoo Kim
158
1
0
23 Feb 2024
Indirect Meltdown: Building Novel Side-Channel Attacks from Transient-Execution Attacks
European Symposium on Research in Computer Security (ESORICS), 2023
Daniel Weber
Fabian Thomas
Lukas Gerlach
Ruiyi Zhang
Michael Schwarz
173
0
0
06 Oct 2023
No Forking Way: Detecting Cloning Attacks on Intel SGX Applications
Asia-Pacific Computer Systems Architecture Conference (ACSA), 2023
Samira Briongos
Ghassan O. Karame
Claudio Soriente
Annika Wilde
186
6
0
04 Oct 2023
Timing the Transient Execution: A New Side-Channel Attack on Intel CPUs
Yu Jin
Pengfei Qiu
Chunlu Wang
Yihao Yang
Dongsheng Wang
Gang Qu
140
3
0
21 Apr 2023
Hacky Racers: Exploiting Instruction-Level Parallelism to Generate Stealthy Fine-Grained Timers
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2022
Haocheng Xiao
S. Ainsworth
SyDa
146
17
0
26 Nov 2022
Write Me and I'll Tell You Secrets -- Write-After-Write Effects On Intel CPUs
International Symposium on Recent Advances in Intrusion Detection (RAID), 2022
Jan Philipp Thoma
Tim Güneysu
131
13
0
05 Sep 2022
AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks
International Symposium on High-Performance Computer Architecture (HPCA), 2022
Mulong Luo
Wenjie Xiong
G. G. Lee
Yueying Li
Xiaomeng Yang
Amy Zhang
Yuandong Tian
Hsien-Hsin S. Lee
G. E. Suh
AAML
245
12
0
17 Aug 2022
Attack of the Knights: A Non Uniform Cache Side-Channel Attack
Asia-Pacific Computer Systems Architecture Conference (ACSA), 2021
Farabi Mahmud
Sungkeun Kim
H. Chawla
Chia-Che Tsai
Eun Jung Kim
A. Muzahid
236
2
0
19 Dec 2021
Adversarial Prefetch: New Cross-Core Cache Side Channel Attacks
IEEE Symposium on Security and Privacy (IEEE S&P), 2021
Yanan Guo
Andrew Zigerelli
Youtao Zhang
Jun Yang
SILM
210
37
0
24 Oct 2021
Util::Lookup: Exploiting key decoding in cryptographic libraries
Conference on Computer and Communications Security (CCS), 2021
Florian Sieck
Sebastian Berndt
Jan Wichelmann
T. Eisenbarth
77
17
0
10 Aug 2021
Osiris: Automated Discovery of Microarchitectural Side Channels
USENIX Security Symposium (USENIX Security), 2021
Daniel Weber
A. Ibrahim
Hamed Nemati
Michael Schwarz
C. Rossow
134
73
0
07 Jun 2021
Abusing Cache Line Dirty States to Leak Information in Commercial Processors
International Symposium on High-Performance Computer Architecture (HPCA), 2021
Yujie Cui
Chun Yang
Xu Cheng
215
17
0
17 Apr 2021
A Survey of Microarchitectural Side-channel Vulnerabilities, Attacks and Defenses in Cryptography
ACM Computing Surveys (CSUR), 2021
Xiaoxuan Lou
Tianwei Zhang
Jun Jiang
Yinqian Zhang
AAML
198
122
0
26 Mar 2021
Prime+Probe 1, JavaScript 0: Overcoming Browser-based Side-Channel Defenses
USENIX Security Symposium (USENIX Security), 2021
A. Shusterman
Ayush Agarwal
Sioli O'Connell
Daniel Genkin
Yossef Oren
Y. Yarom
112
73
0
08 Mar 2021
MIRAGE: Mitigating Conflict-Based Cache Attacks with a Practical Fully-Associative Design
USENIX Security Symposium (USENIX Security), 2020
Gururaj Saileshwar
Moinuddin K. Qureshi
227
98
0
18 Sep 2020
CACHE SNIPER : Accurate timing control of cache evictions
Samira Briongos
Ida Bruhns
Pedro Malagón
T. Eisenbarth
Jose M. Moya
101
1
0
27 Aug 2020
Speculative Interference Attacks: Breaking Invisible Speculation Schemes
International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2020
Mohammad R. Behnia
Prateek Sahu
Riccardo Paccagnella
Jiyong Yu
Zirui Neil Zhao
...
Fangfei Liu
Ron Gabor
Christopher W. Fletcher
A. Basak
Alaa R. Alameldeen
215
86
0
23 Jul 2020
Flushgeist: Cache Leaks from Beyond the Flush
Pepe Vila
Andreas Abel
Marco Guarnieri
Boris Köpf
Jan Reineke
153
10
0
28 May 2020
Survey of Transient Execution Attacks
Wenjie Xiong
Jakub Szefer
SILM
176
26
0
27 May 2020
Leaking Information Through Cache LRU States
International Symposium on High-Performance Computer Architecture (HPCA), 2019
Wenjie Xiong
Jakub Szefer
143
75
0
20 May 2019
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