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SeqL: Secure Scan-Locking for IP Protection
v1v2 (latest)

SeqL: Secure Scan-Locking for IP Protection

IEEE International Symposium on Quality Electronic Design (ISQED), 2020
26 May 2020
S. Potluri
Aydin Aysu
Akash Kumar
ArXiv (abs)PDFHTML

Papers citing "SeqL: Secure Scan-Locking for IP Protection"

5 / 5 papers shown
Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and
  ILP
Unraveling Latch Locking Using Machine Learning, Boolean Analysis, and ILPIEEE International Symposium on Quality Electronic Design (ISQED), 2023
Dake Chen
Xuan Zhou
Yinghua Hu
Yuke Zhang
Kaixin Yang
A. Rittenbach
Pierluigi Nuzzo
Peter A. Beerel
165
2
0
28 Apr 2023
Complexity Analysis of the SAT Attack on Logic Locking
Complexity Analysis of the SAT Attack on Logic LockingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD), 2022
Yadi Zhong
Ujjwal Guin
205
29
0
05 Jul 2022
A Survey on RISC-V Security: Hardware and Architecture
A Survey on RISC-V Security: Hardware and Architecture
Tao Lu
207
50
0
09 Jul 2021
A Novel Topology-Guided Attack and Its Countermeasure Towards Secure
  Logic Locking
A Novel Topology-Guided Attack and Its Countermeasure Towards Secure Logic LockingJournal of Cryptographic Engineering (JCE), 2020
Yuqiao Zhang
Ayush Jain
Pinchen Cui
Ziqi Zhou
Ujjwal Guin
AAML
161
6
0
10 Jun 2020
Efficacy of Satisfiability Based Attacks in the Presence of Circuit
  Reverse Engineering Errors
Efficacy of Satisfiability Based Attacks in the Presence of Circuit Reverse Engineering ErrorsInternational Symposium on Circuits and Systems (ISCAS), 2020
Qinhan Tan
S. Potluri
Aydin Aysu
98
2
0
26 May 2020
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