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A High Throughput Parallel Hash Table on FPGA using XOR-based Memory
v1v2 (latest)

A High Throughput Parallel Hash Table on FPGA using XOR-based Memory

7 August 2021
Ruizhi Zhang
Sasindu Wijeratne
Yang Yang
S. Kuppannagari
Viktor Prasanna
ArXiv (abs)PDFHTML

Papers citing "A High Throughput Parallel Hash Table on FPGA using XOR-based Memory"

1 / 1 papers shown
Title
Reconfigurable Low-latency Memory System for Sparse Matricized Tensor
  Times Khatri-Rao Product on FPGA
Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA
Sasindu Wijeratne
Rajgopal Kannan
Viktor Prasanna
50
6
0
18 Sep 2021
1