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2109.03040
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Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks
21 August 2021
Sasindu Wijeratne
Sandaruwan Jayaweera
Mahesh Dananjaya
A. Pasqual
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Papers citing
"Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks"
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Title
Programmable FPGA-based Memory Controller
Sasindu Wijeratne
S. Pattnaik
Zhiyu Chen
R. Kannan
Viktor Prasanna
15
3
0
21 Aug 2021
1