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Improving DRAM Performance, Security, and Reliability by Understanding
  and Exploiting DRAM Timing Parameter Margins

Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins

29 September 2021
Jeremie S. Kim
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Papers citing "Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM Timing Parameter Margins"

1 / 1 papers shown
Title
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple
  Row Activation in Commodity DRAM Chips
QUAC-TRNG: High-Throughput True Random Number Generation Using Quadruple Row Activation in Commodity DRAM Chips
Ataberk Olgun
Minesh Patel
A. G. Yaglikçi
Haocong Luo
Jeremie S. Kim
Nisa Bostanci
Nandita Vijaykumar
Oguz Ergin
O. Mutlu
25
61
0
19 May 2021
1