RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU

5 October 2021

Papers citing "RASA: Efficient Register-Aware Systolic Array Matrix Engine for CPU"

3 / 3 papers shown

Title
Abstracting Sparse DNN Acceleration via Structured Sparse Tensor Decomposition Geonhwa Jeong Po-An Tsai A. Bambhaniya S. Keckler Tushar Krishna 27 7 0 12 Mar 2024
VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs Geonhwa Jeong S. Damani A. Bambhaniya Eric Qin C. Hughes S. Subramoney Hyesoon Kim T. Krishna MoE 27 24 0 17 Feb 2023
EcoFlow: Efficient Convolutional Dataflows for Low-Power Neural Network Accelerators Lois Orosa Skanda Koppula Yaman Umuroglu Konstantinos Kanellopoulos Juan Gómez Luna Michaela Blott K. Vissers O. Mutlu 38 4 0 04 Feb 2022