 Toward Automated Potential Primary Asset Identification in Verilog DesignsIEEE International Symposium on Quality Electronic Design (ISQED), 2025 |
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 Theoretical Patchability Quantification for IP-Level Hardware Patching
DesignsAsia and South Pacific Design Automation Conference (ASP-DAC), 2023 |
 Chip-Chat: Challenges and Opportunities in Conversational Hardware
DesignWorkshop on Machine Learning for CAD (ML4CAD), 2023 |
 Fixing Hardware Security Bugs with Large Language ModelsIEEE Transactions on Information Forensics and Security (IEEE TIFS), 2023 |
