Hacky Racers: Exploiting Instruction-Level Parallelism to Generate Stealthy Fine-Grained Timers

26 November 2022

Papers citing "Hacky Racers: Exploiting Instruction-Level Parallelism to Generate Stealthy Fine-Grained Timers"

5 / 5 papers shown

Title
Memory Under Siege: A Comprehensive Survey of Side-Channel Attacks on Memory MD Mahady Hassan Shanto Roy Reza Rahaeimehr 41 0 0 08 May 2025
TikTag: Breaking ARM's Memory Tagging Extension with Speculative Execution Juhee Kim Jinbum Park Sihyeon Roh Jaeyoung Chung Youngjoo Lee Taesoo Kim Byoungyoung Lee 27 7 0 13 Jun 2024
New Cross-Core Cache-Agnostic and Prefetcher-based Side-Channels and Covert-Channels Yun Chen Ali Hajiabadi Lingfeng Pei Trevor E. Carlson 13 2 0 19 Jun 2023
"It's a Trap!"-How Speculation Invariance Can Be Abused with Forward Speculative Interference Pavlos Aimoniotis Christos Sakalis Magnus Själander S. Kaxiras 22 2 0 22 Sep 2021
SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free Speculation Khaled N. Khasawneh Esmaeil Mohammadian Koruyeh Chengyu Song Dmitry Evtyushkin D. Ponomarev Nael B. Abu-Ghazaleh 26 183 0 13 Jun 2018