INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search

22 May 2023

Papers citing "INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search"

3 / 3 papers shown

Title
Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs Yingjie Li Mingju Liu Alan Mishchenko Cunxi Yu 37 6 0 09 Nov 2023
OpenABC-D: A Large-Scale Dataset For Machine Learning Guided Integrated Circuit Synthesis A. B. Chowdhury Benjamin Tan Ramesh Karri S. Garg 33 36 0 21 Oct 2021
DRiLLS: Deep Reinforcement Learning for Logic Synthesis Abdelrahman I. Hosny S. Hashemi M. Shalan Sherief Reda 61 109 0 11 Nov 2019