A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design

22 August 2023

Lei Chen

Xing Li

Jianye Hao

Papers citing "A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design"

2 / 2 papers shown

Title
Controlling Overestimation Bias with Truncated Mixture of Continuous Distributional Quantile Critics Arsenii Kuznetsov Pavel Shvechikov Alexander Grishin Dmitry Vetrov 136 184 0 08 May 2020
DRiLLS: Deep Reinforcement Learning for Logic Synthesis Abdelrahman I. Hosny S. Hashemi M. Shalan Sherief Reda 59 109 0 11 Nov 2019