Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs

9 November 2023

Papers citing "Verilog-to-PyG -- A Framework for Graph Learning and Augmentation on RTL Designs"

4 / 4 papers shown

Title
Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformers Raika Karimi Faezeh Faez Yingxue Zhang Xing Li Lei Chen M. Yuan Mahdi Biparva 52 0 0 16 Sep 2024
MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization Faezeh Faez Raika Karimi Yingxue Zhang Xing Li Lei Chen M. Yuan Mahdi Biparva 17 2 0 09 Sep 2024
BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation Yingjie Li Anthony Agnesina Yanqing Zhang Haoxing Ren Cunxi Yu 19 1 0 19 Jan 2024
ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning A. B. Chowdhury Lilas Alrahis L. Collini J. Knechtel Ramesh Karri S. Garg Ozgur Sinanoglu Benjamin Tan AAML 29 6 0 06 Mar 2023