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Advanced Large Language Model (LLM)-Driven Verilog Development:
  Enhancing Power, Performance, and Area Optimization in Code Synthesis

Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis

2 December 2023
Kiran Thorat
Jiahui Zhao
Yaotian Liu
Hongwu Peng
Xi Xie
Bin Lei
Jeff Zhang
Caiwen Ding
ArXivPDFHTML

Papers citing "Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis"

3 / 3 papers shown
Title
RocketPPA: Ultra-Fast LLM-Based PPA Estimator at Code-Level Abstraction
RocketPPA: Ultra-Fast LLM-Based PPA Estimator at Code-Level Abstraction
Armin Abdollahi
M. Kamal
Massoud Pedram
MoE
59
1
0
27 Mar 2025
Chip-Chat: Challenges and Opportunities in Conversational Hardware
  Design
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
Jason Blocklove
S. Garg
Ramesh Karri
Hammond Pearce
38
164
0
22 May 2023
DRiLLS: Deep Reinforcement Learning for Logic Synthesis
DRiLLS: Deep Reinforcement Learning for Logic Synthesis
Abdelrahman I. Hosny
S. Hashemi
M. Shalan
Sherief Reda
56
109
0
11 Nov 2019
1