Evaluating LLMs for Hardware Design and Test

23 April 2024

Papers citing "Evaluating LLMs for Hardware Design and Test"

5 / 5 papers shown

Title
Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead Guang Yang Wei-Shi Zheng Xiang Chen Dong Liang Peng Hu ... Haotian Cheng Yiheng Shen Xing Hu Terry Yue Zhuo David Lo 24 0 0 29 Oct 2025
Large Language Models (LLMs) for Electronic Design Automation (EDA) K. Xu Denis Schwachhofer Jason Blocklove I. Polian P. Domanski ... Ozgur Sinanoglu J. Knechtel Zhuorui Zhao Ulf Schlichtmann Bing Li 73 2 0 27 Aug 2025
Deep Representation Learning for Electronic Design Automation Pratik Shrestha Saran Phatharodom Alec Aversa David Blankenship Zhengfeng Wu Ioannis Savidis 310 0 0 04 May 2025
Hardware Design and Security Needs Attention: From Survey to Path Forward Matthew William Redondo Muhtasim Alam Chowdhury B. S. Latibari M. Mamun Jaeden Wolf Carpenter Benjamin Tan Hammond Pearce Pratik Satam Soheil Salehi Soheil Salehi 3DV 273 3 0 11 Apr 2025
Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective Luca Collini Andrew Hennessee Ramesh Karri Siddharth Garg ELM LRM 191 7 0 17 Mar 2025