Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation

11 July 2024

ArXiv (abs)PDF HTML Github (38★)

Papers citing "Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation"

9 / 9 papers shown

ChipMind: Retrieval-Augmented Reasoning for Long-Context Circuit Design Specifications

...

305

05 Dec 2025

Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead

...

174

29 Oct 2025

AnalogCoder-Pro: Unifying Analog Circuit Generation and Optimization via Multi-modal LLMs

282

04 Aug 2025

RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs

...

145

22 Jul 2025

Hardware Design and Security Needs Attention: From Survey to Path Forward

Matthew William Redondo

Muhtasim Alam Chowdhury

B. S. Latibari

M. Mamun

Jaeden Wolf Carpenter

371

11 Apr 2025

ML For Hardware Design Interpretability: Challenges and Opportunities

234

11 Apr 2025

BRIDGES: Bridging Graph Modality and Large Language Models within EDA Tasks

277

07 Apr 2025

DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation ModelInternational Conference on Learning Representations (ICLR), 2025

374

20 Feb 2025

Are LLMs Any Good for High-Level Synthesis?International Conference on Computer Aided Design (ICCAD), 2024

Yuchao Liao

Tosiron Adegbija

Roman L. Lysecky

245

19 Aug 2024