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2407.18276
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Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design
23 July 2024
Andre Nakkab
Sai Qian Zhang
Ramesh Karri
Siddharth Garg
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Papers citing
"Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design"
4 / 4 papers shown
Title
Can Reasoning Models Reason about Hardware? An Agentic HLS Perspective
L. Collini
Andrew Hennessee
Ramesh Karri
Siddharth Garg
ELM
LRM
35
0
0
17 Mar 2025
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
Bardia Nadimi
Ghali Omar Boutaib
Hao Zheng
51
1
0
15 Mar 2025
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
Jason Blocklove
S. Garg
Ramesh Karri
Hammond Pearce
38
164
0
22 May 2023
CodeT5: Identifier-aware Unified Pre-trained Encoder-Decoder Models for Code Understanding and Generation
Yue Wang
Weishi Wang
Shafiq R. Joty
S. Hoi
201
1,451
0
02 Sep 2021
1