Papers
Communities
Events
Blog
Pricing
Search
Open menu
Home
Papers
2502.12732
Cited By
Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment
18 February 2025
Haoyuan Wu
Haisheng Zheng
Yuan Pu
Bei Yu
Re-assign community
ArXiv
PDF
HTML
Papers citing
"Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment"
1 / 1 papers shown
Title
Architect of the Bits World: Masked Autoregressive Modeling for Circuit Generation Guided by Truth Table
Haoyuan Wu
Haisheng Zheng
Shoubo Hu
Zhuolun He
Bei Yu
45
0
0
18 Feb 2025
1