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Architect of the Bits World: Masked Autoregressive Modeling for Circuit Generation Guided by Truth Table
v1v2 (latest)

Architect of the Bits World: Masked Autoregressive Modeling for Circuit Generation Guided by Truth Table

18 February 2025
Haoyuan Wu
Haisheng Zheng
Shoubo Hu
Zhuolun He
Bei Yu
ArXiv (abs)PDFHTML

Papers citing "Architect of the Bits World: Masked Autoregressive Modeling for Circuit Generation Guided by Truth Table"

1 / 1 papers shown
Title
Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment
Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG AlignmentInternational Conference on Learning Representations (ICLR), 2025
Haoyuan Wu
Haisheng Zheng
Yuan Pu
Bei Yu
202
6
0
18 Feb 2025
1