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Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs

Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs

28 April 2025
Muhammad Sabih
Abrarul Karim
Jakob Wittmann
Frank Hannig
J. Teich
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Papers citing "Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs"

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