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Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators

Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators

IEEE International Symposium on Quality Electronic Design (ISQED), 2025
26 February 2026
Yuhao Liu
Salim Ullah
Akash Kumar
    MQ
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