MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications

3 March 2024

Papers citing "MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications"

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Title
Dynamic Tsetlin Machine Accelerators for On-Chip Training at the Edge using FPGAs Gang Mao Tousif Rahman Sidharth Maheshwari Bob Pattison Zhuang Shao Rishad Shafik Alex Yakovlev 73 0 0 28 Apr 2025
Runtime Tunable Tsetlin Machines for Edge Inference on eFPGAs Tousif Rahman Gang Mao Bob Pattison Sidharth Maheshwari Marcos Sartori A. Wheeldon Rishad Shafik Alex Yakovlev 83 0 0 10 Feb 2025