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CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization

CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization

15 July 2024
Yang Zhao
Di Huang
Chongxiao Li
Pengwei Jin
Ziyuan Nan
Tianyun Ma
Lei Qi
Yansong Pan
Zhenxing Zhang
Lei Qi
Xishan Zhang
Zidong Du
Rui Zhang
Xingui Hu
Yunji Chen
Qi Guo
Xing Hu
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Papers citing "CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization"

22 / 22 papers shown
Title
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
N. Wang
Bingkun Yao
Jie Zhou
Yuchen Hu
Xi Wang
Nan Guan
Zhe Jiang
OffRL
17
0
0
22 Apr 2025
ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model
ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model
Haiyan Qin
Zhiwei Xie
Jingjing Li
Liangchen Li
Xiaotong Feng
J. Liu
Wang Kang
OffRL
LRM
30
0
0
20 Apr 2025
Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligence
Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligence
Haiyan Qin
Jiahao Feng
Xiaotong Feng
Wei W. Xing
Wang Kang
22
0
0
20 Apr 2025
RTLRepoCoder: Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentation
RTLRepoCoder: Repository-Level RTL Code Completion through the Combination of Fine-Tuning and Retrieval Augmentation
Peiyang Wu
Nan Guo
Junliang Lv
Xiao Xiao
Xiaochun Ye
21
1
0
11 Apr 2025
Hardware Design and Security Needs Attention: From Survey to Path Forward
Hardware Design and Security Needs Attention: From Survey to Path Forward
Sujan Ghimire
Muhtasim Alam Chowdhury
B. S. Latibari
M. Mamun
Jaeden Wolf Carpenter
Benjamin Tan
Hammond Pearce
Pratik Satam
Soheil Salehi
3DV
34
0
0
11 Apr 2025
TuRTLe: A Unified Evaluation of LLMs for RTL Generation
TuRTLe: A Unified Evaluation of LLMs for RTL Generation
Dario Garcia-Gasulla
Gokcen Kestor
Emanuele Parisi
Miquel Albertí-Binimelis
Cristian Gutierrez
Razine Moundir Ghorab
Orlando Montenegro
Bernat Homs
Miquel Moreto
35
0
0
31 Mar 2025
HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL
HDLCoRe: A Training-Free Framework for Mitigating Hallucinations in LLM-Generated HDL
Heng Ping
Shixuan Li
Peiyu Zhang
Anzhe Cheng
Shukai Duan
...
Xiongye Xiao
Wei Yang
Shahin Nazarian
Andrei Irimia
Paul Bogdan
42
1
0
18 Mar 2025
Speculative Decoding for Verilog: Speed and Quality, All in One
Speculative Decoding for Verilog: Speed and Quality, All in One
Changran Xu
Yi Liu
Yunhao Zhou
Shan Huang
Ningyi Xu
Qiang Xu
45
0
0
18 Mar 2025
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
VeriMind: Agentic LLM for Automated Verilog Generation with a Novel Evaluation Metric
Bardia Nadimi
Ghali Omar Boutaib
Hao Zheng
40
1
0
15 Mar 2025
Enhancing Large Language Models for Hardware Verification: A Novel SystemVerilog Assertion Dataset
Anand Menon
Samit S Miftah
Shamik Kundu
Souvik Kundu
Amisha Srivastava
Arnab Raha
Gabriel Theodor Sonnenschein
Suvadeep Banerjee
Deepak A. Mathaikutty
K. Basu
39
0
0
11 Mar 2025
DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis
DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis
Z. Li
Changran Xu
Zhengyuan Shi
Zedong Peng
Yi Liu
...
X. Wang
Jieru Zhao
Zhufei Chu
X. J. Yang
Qiang Xu
49
3
0
25 Feb 2025
The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation
The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation
Reza Moravej
Saurabh Bodhe
Zhanguang Zhang
Didier Chetelat
Dimitrios Tsaras
Yingxue Zhang
Hui-Ling Zhen
Jianye Hao
M. Yuan
45
1
0
17 Feb 2025
OpenCodeInterpreter: Integrating Code Generation with Execution and Refinement
OpenCodeInterpreter: Integrating Code Generation with Execution and Refinement
Tianyu Zheng
Ge Zhang
Tianhao Shen
Xueling Liu
Bill Yuchen Lin
Jie Fu
Wenhu Chen
Xiang Yue
SyDa
67
102
0
08 Jan 2025
PromptV: Leveraging LLM-powered Multi-Agent Prompting for High-quality
  Verilog Generation
PromptV: Leveraging LLM-powered Multi-Agent Prompting for High-quality Verilog Generation
Zhendong Mi
Renming Zheng
Haowen Zhong
Yue Sun
Shaoyi Huang
66
0
0
15 Dec 2024
CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair
CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair
Mingjie Liu
Yun-Da Tsai
Wenfei Zhou
Haoxing Ren
SyDa
3DV
33
3
0
19 Sep 2024
AIvril: AI-Driven RTL Generation With Verification In-The-Loop
AIvril: AI-Driven RTL Generation With Verification In-The-Loop
Mubashir ul Islam
Humza Sami
P. Gaillardon
V. Tenace
34
5
0
03 Sep 2024
ITERTL: An Iterative Framework for Fine-tuning LLMs for RTL Code Generation
Peiyang Wu
Nan Guo
Xiao Xiao
Wenming Li
Xiaochun Ye
Dongrui Fan
22
0
0
28 Jun 2024
Chip-Chat: Challenges and Opportunities in Conversational Hardware
  Design
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
Jason Blocklove
S. Garg
Ramesh Karri
Hammond Pearce
38
164
0
22 May 2023
Is Your Code Generated by ChatGPT Really Correct? Rigorous Evaluation of
  Large Language Models for Code Generation
Is Your Code Generated by ChatGPT Really Correct? Rigorous Evaluation of Large Language Models for Code Generation
Jiawei Liu
Chun Xia
Yuyao Wang
Lingming Zhang
ELM
ALM
161
388
0
02 May 2023
Training language models to follow instructions with human feedback
Training language models to follow instructions with human feedback
Long Ouyang
Jeff Wu
Xu Jiang
Diogo Almeida
Carroll L. Wainwright
...
Amanda Askell
Peter Welinder
Paul Christiano
Jan Leike
Ryan J. Lowe
OSLM
ALM
301
11,730
0
04 Mar 2022
Multitask Prompted Training Enables Zero-Shot Task Generalization
Multitask Prompted Training Enables Zero-Shot Task Generalization
Victor Sanh
Albert Webson
Colin Raffel
Stephen H. Bach
Lintang Sutawika
...
T. Bers
Stella Biderman
Leo Gao
Thomas Wolf
Alexander M. Rush
LRM
203
1,651
0
15 Oct 2021
CodeT5: Identifier-aware Unified Pre-trained Encoder-Decoder Models for
  Code Understanding and Generation
CodeT5: Identifier-aware Unified Pre-trained Encoder-Decoder Models for Code Understanding and Generation
Yue Wang
Weishi Wang
Shafiq R. Joty
S. Hoi
196
1,451
0
02 Sep 2021
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