RTLLM: An Open-Source Benchmark for Design RTL Generation with Large
Language Model

RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

10 August 2023

Papers citing "RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model"

12 / 12 papers shown

Title
ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Haiyan Qin Zhiwei Xie Jingjing Li Liangchen Li Xiaotong Feng J. Liu Wang Kang OffRL LRM 48 0 0 20 Apr 2025
Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligence Haiyan Qin Jiahao Feng Xiaotong Feng Wei W. Xing Wang Kang 27 0 0 20 Apr 2025
RocketPPA: Ultra-Fast LLM-Based PPA Estimator at Code-Level Abstraction Armin Abdollahi M. Kamal Massoud Pedram MoE 59 1 0 27 Mar 2025
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding Zeng Wang Minghao Shao M. Nabeel P. Roy Likhitha Mankali Jitendra Bhandari Ramesh Karri Ozgur Sinanoglu Muhammad Shafique J. Knechtel 63 0 0 17 Mar 2025
ResBench: Benchmarking LLM-Generated FPGA Designs with Resource Awareness Ce Guo Tong Zhao 61 1 0 11 Mar 2025
TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator Deepak Vungarala Mohammed E. Elbtity Sumiya Syed Sakila Alam Kartik Pandit Arnob Ghosh Ramtin Zand Shaahin Angizi 29 1 0 07 Mar 2025
The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation Reza Moravej Saurabh Bodhe Zhanguang Zhang Didier Chetelat Dimitrios Tsaras Yingxue Zhang Hui-Ling Zhen Jianye Hao M. Yuan 50 1 0 17 Feb 2025
CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair Mingjie Liu Yun-Da Tsai Wenfei Zhou Haoxing Ren SyDa 3DV 45 3 0 19 Sep 2024
CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization Yang Zhao Di Huang Chongxiao Li Pengwei Jin Ziyuan Nan ... Rui Zhang Xingui Hu Yunji Chen Qi Guo Xing Hu 64 22 0 15 Jul 2024
LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust Zeng Wang Lilas Alrahis Likhitha Mankali J. Knechtel Ozgur Sinanoglu 34 9 0 11 May 2024
LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation Zixi Zhang Greg Chadwick Hugo McNally Yiren Zhao Robert D. Mullins Jianyi Cheng Robert Mullins Yiren Zhao 21 18 0 06 Oct 2023
Chip-Chat: Challenges and Opportunities in Conversational Hardware Design Jason Blocklove S. Garg Ramesh Karri Hammond Pearce 38 164 0 22 May 2023