Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on
Embedded FPGAs

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs

21 November 2018

Tianjun Zhang

Giulio Gambardella

Luciano Lavagno

Papers citing "Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs"

8 / 8 papers shown

Title
Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design Jian Meng Yuan Liao Anupreetham Anupreetham Ahmed Hassan Shixing Yu Han-Sok Suh Xiaofeng Hu Jae-sun Seo MQ 49 1 0 02 May 2024
Hardware Accelerator and Neural Network Co-Optimization for Ultra-Low-Power Audio Processing Devices Christoph Gerum Adrian Frischknecht T. Hald Paul Palomero Bernardo Konstantin Lubeck Oliver Bringmann 37 10 0 08 Sep 2022
Vis-TOP: Visual Transformer Overlay Processor Wei Hu Dian Xu Zimeng Fan Fang Liu Yanxiang He BDL ViT 20 5 0 21 Oct 2021
How Do Adam and Training Strategies Help BNNs Optimization? Zechun Liu Zhiqiang Shen Shichao Li K. Helwegen Dong Huang Kwang-Ting Cheng ODL MQ 22 82 0 21 Jun 2021
Rethinking Co-design of Neural Architectures and Hardware Accelerators Yanqi Zhou Xuanyi Dong Berkin Akin Mingxing Tan Daiyi Peng Tianjian Meng Amir Yazdanbakhsh Da Huang Ravi Narayanaswami James Laudon 49 26 0 17 Feb 2021
Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization Framework Sung-En Chang Yanyu Li Mengshu Sun Runbin Shi Hayden Kwok-Hay So Xuehai Qian Yanzhi Wang Xue Lin MQ 18 82 0 08 Dec 2020
4-Connected Shift Residual Networks Andrew Brown Pascal Mettes M. Worring 3DPC 15 8 0 22 Oct 2019
Automatic Compiler Based FPGA Accelerator for CNN Training S. Venkataramanaiah Yufei Ma Shihui Yin Eriko Nurvitadhi A. Dasu Yu Cao Jae-sun Seo 16 38 0 15 Aug 2019