VerilogEval: Evaluating Large Language Models for Verilog Code Generation

14 September 2023

Papers citing "VerilogEval: Evaluating Large Language Models for Verilog Code Generation"

50 / 85 papers shown

Title
Deep Representation Learning for Electronic Design Automation Pratik Shrestha Saran Phatharodom Alec Aversa David Blankenship Zhengfeng Wu Ioannis Savidis 17 0 0 04 May 2025
LIFT: LLM-Based Pragma Insertion for HLS via GNN Supervised Fine-Tuning Neha Prakriya Zijian Ding Yizhou Sun Jason Cong 21 0 0 29 Apr 2025
VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction N. Wang Bingkun Yao Jie Zhou Yuchen Hu Xi Wang Nan Guan Zhe Jiang 31 0 0 27 Apr 2025
VeriCoder: Enhancing LLM-Based RTL Code Generation through Functional Correctness Validation Anjiang Wei Huanmi Tan Tarun Suresh Daniel Mendoza Thiago S. F. X. Teixeira Ke Wang Caroline Trippel Alex Aiken OffRL 16 0 0 22 Apr 2025
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback N. Wang Bingkun Yao Jie Zhou Yuchen Hu Xi Wang Nan Guan Zhe Jiang OffRL 22 0 0 22 Apr 2025
ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model Haiyan Qin Zhiwei Xie Jingjing Li Liangchen Li Xiaotong Feng J. Liu Wang Kang OffRL LRM 48 0 0 20 Apr 2025
Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligence Haiyan Qin Jiahao Feng Xiaotong Feng Wei W. Xing Wang Kang 27 0 0 20 Apr 2025
Evolution of Optimization Algorithms for Global Placement via Large Language Models Xufeng Yao Jiaxi Jiang Yuxuan Zhao Peiyu Liao Yibo Lin Bei Yu 52 0 0 18 Apr 2025
HLS-Eval: A Benchmark and Framework for Evaluating LLMs on High-Level Synthesis Design Tasks Stefan Abi-Karam Cong Hao ELM 31 0 0 16 Apr 2025
SymRTLO: Enhancing RTL Code Optimization with LLMs and Neuron-Inspired Symbolic Reasoning Yiting Wang Wanghao Ye Ping Guo Yexiao He Z. Wang ... Sihan Chen Ankur Srivastava Qingfu Zhang Gang Qu Ang Li 35 0 0 14 Apr 2025
GenEDA: Unleashing Generative Reasoning on Netlist via Multimodal Encoder-Decoder Aligned Foundation Model Wenji Fang Jing Wang Yao Lu Shang Liu Zhiyao Xie AI4CE 34 1 0 13 Apr 2025
Hardware Design and Security Needs Attention: From Survey to Path Forward Sujan Ghimire Muhtasim Alam Chowdhury B. S. Latibari M. Mamun Jaeden Wolf Carpenter Benjamin Tan Hammond Pearce Pratik Satam Soheil Salehi 3DV 36 0 0 11 Apr 2025
BRIDGES: Bridging Graph Modality and Large Language Models within EDA Tasks Wei Li Yang Zou Christopher Ellis Ruben Purdy Shawn Blanton José M. F. Moura 21 0 0 07 Apr 2025
TuRTLe: A Unified Evaluation of LLMs for RTL Generation Dario Garcia-Gasulla Gokcen Kestor Emanuele Parisi Miquel Albertí-Binimelis Cristian Gutierrez Razine Moundir Ghorab Orlando Montenegro Bernat Homs Miquel Moreto 40 0 0 31 Mar 2025
NLS: Natural-Level Synthesis for Hardware Implementation Through GenAI Kaiyuan Yang Huang Ouyang X. Wang Bingjie Lu Yanbo Wang Charith Abhayaratne Sizhao Li Long Jin Tiantai Deng 33 0 0 28 Mar 2025
RocketPPA: Ultra-Fast LLM-Based PPA Estimator at Code-Level Abstraction Armin Abdollahi M. Kamal Massoud Pedram MoE 59 1 0 27 Mar 2025
Speculative Decoding for Verilog: Speed and Quality, All in One Changran Xu Yi Liu Yunhao Zhou Shan Huang Ningyi Xu Qiang Xu 48 0 0 18 Mar 2025
VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding Zeng Wang Minghao Shao M. Nabeel P. Roy Likhitha Mankali Jitendra Bhandari Ramesh Karri Ozgur Sinanoglu Muhammad Shafique J. Knechtel 63 0 0 17 Mar 2025
ResBench: Benchmarking LLM-Generated FPGA Designs with Resource Awareness Ce Guo Tong Zhao 61 1 0 11 Mar 2025
TPU-Gen: LLM-Driven Custom Tensor Processing Unit Generator Deepak Vungarala Mohammed E. Elbtity Sumiya Syed Sakila Alam Kartik Pandit Arnob Ghosh Ramtin Zand Shaahin Angizi 29 1 0 07 Mar 2025
AnalogGenie: A Generative Engine for Automatic Discovery of Analog Circuit Topologies Jian Gao Weidong Cao Junyi Yang Xuan Zhang 42 1 0 28 Feb 2025
Are LLMs Ready for Practical Adoption for Assertion Generation? Vaishnavi Pulavarthi Deeksha Nandal Soham Dan Debjit Pal 51 2 0 28 Feb 2025
Nexus: A Lightweight and Scalable Multi-Agent Framework for Complex Tasks Automation Humza Sami Mubashir ul Islam Samy Charas Asav Gandhi P. Gaillardon V. Tenace LLMAG 69 0 0 26 Feb 2025
DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis Z. Li Changran Xu Zhengyuan Shi Zedong Peng Yi Liu ... X. Wang Jieru Zhao Zhufei Chu X. J. Yang Qiang Xu 54 3 0 25 Feb 2025
DeepRTL: Bridging Verilog Understanding and Generation with a Unified Representation Model Yi Liu Changran Xu Yunhao Zhou Z. Li Qiang Xu VLM 40 4 0 20 Feb 2025
Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis Jiahao Gai Chen Zhican Wang Hongyu Zhou Wanru Zhao Nicholas D. Lane Hongxiang Fan 44 1 0 19 Feb 2025
The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation Reza Moravej Saurabh Bodhe Zhanguang Zhang Didier Chetelat Dimitrios Tsaras Yingxue Zhang Hui-Ling Zhen Jianye Hao M. Yuan 50 1 0 17 Feb 2025
Self-Supervised Graph Contrastive Pretraining for Device-level Integrated Circuits Sungyoung Lee Z. Wang Seunggeun Kim Taekyun Lee David Z. Pan SSL GNN 76 0 0 13 Feb 2025
A Survey of Research in Large Language Models for Electronic Design Automation Jingyu Pan Guanglei Zhou Chen-Chia Chang Isaac Jacobson Jiang Hu Y. Chen 64 2 0 17 Jan 2025
RTLMarker: Protecting LLM-Generated RTL Copyright via a Hardware Watermarking Framework Kun Wang Kaiyan Chang Mengdi Wang Xinqi Zou Haobo Xu Yinhe Han Ying Wang WaLM 42 1 0 05 Jan 2025
Formal Mathematical Reasoning: A New Frontier in AI Kaiyu Yang Gabriel Poesia Jingxuan He Wenda Li Kristin Lauter Swarat Chaudhuri Dawn Song LRM AI4CE 82 20 0 20 Dec 2024
HPC-Coder-V2: Studying Code LLMs Across Low-Resource Parallel Languages Aman Chaturvedi Daniel Nichols Siddharth Singh A. Bhatele 75 1 0 19 Dec 2024
PromptV: Leveraging LLM-powered Multi-Agent Prompting for High-quality Verilog Generation Zhendong Mi Renming Zheng Haowen Zhong Yue Sun Shaoyi Huang 74 0 0 15 Dec 2024
RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation Lakshmi Likhitha Mankali Jitendra Bhandari Manaar Alam Ramesh Karri Michail Maniatakos Ozgur Sinanoglu J. Knechtel 64 2 0 26 Nov 2024
Neural Model Checking Mirco Giacobbe Daniel Kroening Abhinandan Pal Michael Tautschnig NAI 24 1 0 31 Oct 2024
SPICEPilot: Navigating SPICE Code Generation and Simulation with AI Guidance Deepak Vungarala Sakila Alam Arnob Ghosh Shaahin Angizi 27 3 0 27 Oct 2024
FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware Minwoo Kang Mingjie Liu Ghaith Bany Hamad Syed Suhaib Haoxing Ren LRM 11 1 0 15 Oct 2024
CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair Mingjie Liu Yun-Da Tsai Wenfei Zhou Haoxing Ren SyDa 3DV 45 5 0 19 Sep 2024
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization Xufeng Yao Yiwen Wang Xing Li Yingzhao Lian Ran Chen Lei Chen M. Yuan Hong Xu Bei Yu 32 8 0 04 Sep 2024
AIvril: AI-Driven RTL Generation With Verification In-The-Loop Mubashir ul Islam Humza Sami P. Gaillardon V. Tenace 42 5 0 03 Sep 2024
Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation N. Pinckney Christopher Batten Mingjie Liu Haoxing Ren Brucek Khailany ELM VLM 24 5 0 20 Aug 2024
Are LLMs Any Good for High-Level Synthesis? Yuchao Liao Tosiron Adegbija Roman L. Lysecky 21 0 0 19 Aug 2024
HDL-GPT: High-Quality HDL is All You Need Bhuvnesh Kumar Saurav Nanda G. Parthasarathy Pawan Patil Austin Tsai Parivesh Choudhary LM&MA 23 0 0 25 Jul 2024
Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design Andre Nakkab Sai Qian Zhang Ramesh Karri Siddharth Garg 38 10 0 23 Jul 2024
OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection Fan Cui Chenyang Yin Kexing Zhou You-lin Xiao Guangyu Sun ... Demin Song Dahua Lin Xingcheng Zhang Yun Yun Liang 29 13 0 23 Jul 2024
AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs Mingzhe Gao Jieru Zhao Zhe Lin Wenchao Ding Xiaofeng Hou Yu Feng Chao Li Minyi Guo OffRL 22 10 0 21 Jul 2024
IICPilot: An Intelligent Integrated Circuit Backend Design Framework Using Open EDA Zesong Jiang Qing Zhang Cheng Liu Long Cheng Huawei Li Xiaowei Li 35 2 0 17 Jul 2024
CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization Yang Zhao Di Huang Chongxiao Li Pengwei Jin Ziyuan Nan ... Rui Zhang Xingui Hu Yunji Chen Qi Guo Xing Hu 64 22 0 15 Jul 2024
Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation Kaiyan Chang Zhirong Chen Yunhao Zhou Wenlong Zhu Kun Wang ... Mengdi Wang Shengwen Liang Huawei Li Yinhe Han Ying Wang 37 5 0 11 Jul 2024
MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation Yongan Zhang Zhongzhi Yu Yonggan Fu Cheng Wan Yingyan Celine Lin 27 20 0 02 Jul 2024